pll的翻译

aiming at the 155mb/ s up-stream velocity of atm-pon system, we design the circuit of the burst-mode optical transmitter. we make the frequency synthesis of the pll ( phase-locked loop) get 155mb/ s clock source.

对于PON系统，针对上行传输速率为155Mb/s时，对突发模式光发射机作了电路设计，在电路设计中采用锁相环频率合成器产生155MHz时钟源系统。

before we can setout to find the optimal configuration for our pll, we need to first consider how we find any configuration for our pll.

在我们准备为锁相环找到最优配置之前，首先要考虑如何找到锁相环的所有配置。

This paper discusses the theory of the ∑-△ digital modulation and introduces how to use the theory to the decimal fraction frequency-diving PLL to improve the phase sparing by using the noise adjust function of the multi-step ∑-△ modulation.

本文分析了∑-△数字调制技术的工作原理，把该技术应用于小数分频锁相环中，利用多阶∑-△调制器的噪声整形功能来改善小数分频引起的相位杂散。